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Since the early 1980s, when schematic capture was introduced as an ef cient way to design very large-scale integration (VLSI) circuits, it has been the design method of choice for designers in the world of VLSI design. However, the use of this method reached its limits in the early 1990s, as more and more logic functionality and features were integrated onto a single chip. Today, most application-speci c integrated circuit (ASIC) chips consist of no fewer than one million transistors. Designing circuits this large using the method of schematic capture is time consuming and is no longer ef cient. Therefore, a more ef cient manner of design was required. This new method had to increase the designers ef ciency and allow ease of design, even when dealing with large circuits. From this requirement arose the wide acceptance of HDL (hardware description language). HDL allows a designer to describe the functionality of a required logic circuit in a language that is easy to understand. The description is then simulated using test benches. After the HDL description is veri ed for logic functionality, it is synthesized to logic gates by using synthesis tools. This method helps a designer to design a circuit in a shorter timeframe. The savings in design time is achieved because the designer need not be concerned with the intricate complexities that exist in a particular circuit, but instead is focused on the functionality that is required. This new method of design has been widely adopted today in the eld of ASIC design. It allows designers to design large numbers of logic gates to implement logic features and functionality that are required on an ASIC chip.

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The Modifiers Patch/Spline Editing Edit Spline modifier (mentioned at the start of the chapter) makes spline objects so they can be edited. It has all the same features as the Editable Spline object. The Edit Spline modifier isn t really a modifier, but an Object type. It shows up in the Modifier Stack above the base object. The key benefit of the Edit Spline modifier is that it enables you to edit spline subobjects while maintaining the parametric nature of the primitive object.

Figure 2.27 The Bode diagram for the system From the above Bode diagram the stability margins for the system are de ned as follows. Gain margin: The gain increase that would result in the gain curve crossing the 0 dB line at the frequency corresponding to 180 degrees of open loop phase lag. Phase margin: The additional phase lag that would result in 180 degrees of open loop phase lag at the frequency corresponding to 0 dB of open loop gain. In our example, the gain and phase margins shown on Figure 2.27 are approximately 14 dB and 30 degrees respectively. In practical terms this means that if the open loop gain was increased by 14 dB, which is a factor of about ve, the system would be unstable. Similarly if an additional phase lag of 30 degrees were to be present at a frequency of 1 radian per second the system would be unstable. As a general guide, good design practice is to aim for a minimum of 6 dB (i.e. a factor of two) gain margin and a phase margin of 45 degrees. In our case the gain margin is very good at about 15 dB but the phase margin

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